High-speed LPDDR Signal Acquisition and Decoding Using FPGA

Global

Supervision: Ali Abbasi

Start date: as soon as possible

Duration: 6 month

More details: [JESD209 Standard]

Description

From critical infrastructure to consumer electronics, embedded systems are all around us, underpinning the technological fabric of everyday life. In this thesis, we propose a signal acquisition infrastructure for receiving and decoding LPDDR communication of embedded systems. This includes simple address decoding and more complex data decoding. The instructions for decoding the signals are already well documented in JEDEC JESD 209 standard. Therefore the main tasks for this thesis are the followings:

  1. Acquiring the signal from the memory bus while preserving the signal integrity (e.g., using a differential amplifier).
  2. Decoding both address and data line from LPDDR memory using high-end FPGA.
  3. Optimizing signal decoder implementation to be compatible with JESD209B up to JESD209-4C.

All equipments, interposers, FPGAs related to this project will be provided by the SYSSEC chair.

Requirements

The student is expected to have a background on electrical engineering concepts, High-speed signal acquisition, and isolation, as well as FPGA programming and VHDL.